With the latest popularization of mobile terminals, there have been an increasing demand for miniaturization of semiconductor devices and low power consumption. Under the circumstances, there have arisen a strong need for non-volatile memories for use in such mobile terminals.
As a non-volatile memory, flush memories and ferroelectric random access memories (FeRAM) have presently come into practical use. Since miniaturization of mobile terminals needs to be promoted, a non-volatile memory is sometimes incorporated in a silicon device.
In data processing elements having silicon as a main constituent, not only miniaturization and low power consumption but also high speed operation is required, and therefore, it becomes a task to find how to perform high speed data processing with a small-sized device and low power consumption.
Typical flash memories working as a non-volatile memory perform writing operation at slow speeds and require high voltage. Therefore, they are not suited for use as a non-volatile memory housed in a mobile terminal.
On the other hand, ferroelectric random access memories can perform higher speed operation with lower power consumption, compared to flash memories. However, ferroelectric random access memories present the problem that when they are incorporated in a silicon device, the decomposition temperature of ferroelectric substances is high and a precious metal such as platinam (Pt) is required for forming the electrodes, resulting in an increase in the processing cost.
In cases where a non-volatile memory is not incorporated in a silicon device and a circuit is constructed with an externally disposed non-volatile memory, the packaging area required increases so that a miniaturized and light-weight device cannot be attained. Another problem is such that since the operation speed of a logic device composed of a silicon device is higher than that of the non-volatile memory, the input/output of data to and from the non-volatile memory causes speed overhead.
As a circuit configuration which combines the advantages of high speed operation by a silicon device and the non-volatility of a non-volatile memory, there have been proposed non-volatile circuits such as disclosed in Japanese Patent Kokai Publications No. 2000-293889 and No. 2000-48576.
According to these publications, a flip flop (FF) circuit commonly used in a silicon device and a ferroelectric capacitor are combined and high speed operations are performed under normal operating conditions similarly to the conventional silicon logic devices and when the need arises, writing of data into the ferroelectric capacitor is performed.
The details of Japanese Patent Kokai Publications No. 2000-293889 will be described below. FIG. 13 is a circuit diagram showing a configuration of a prior art non-volatile memory. As shown in FIG. 13, two inverters 101, 102 constitute a flip flop 103 with their inputs and outputs being connected to each other. In the flip flop 103, two nodes Q0, Q1 are connected to bit lines BLN, BLT through NMOS transistors M0, M1 respectively, the NMOS transistors functioning as a transfer gate. The gate electrodes of the NMOS transistors M0, M1 are connected to a common word line WL.
Ferroelectric capacitors F0, F1, which are connected to a common plate line PL at one end, are connected to the nodes Q0, Q1 respectively. The plate line PL is connected to a plate line driving circuit 104.
Although Japanese Patent Kokai Publication No. 2000-48576 uses FETs provided between the node Q0 and the ferroelectric capacitor F0 and between the node Q1 and the ferroelectric capacitor F1, the basic configuration employing the ferroelectric capacitors F0, F1 is common to these publications No. 2000-293889 and No. 2000-48576.
The conventional non-volatile memories of the above-described structures perform operations similar to those of general flip flops under normal operating conditions. When electric power is turned OFF, writing (storing) of data into the ferroelectric capacitors F0, F1 is executed. In this case, the plate line PL which is normally set to ½Vcc (power source voltage) is set to Vcc, so that opposite electric fields are applied to the pair of ferroelectric capacitors F0, F1 respectively according to the potentials of the nodes Q0, Q1. Accordingly, the pair of ferroelectric capacitors F0, F1 are oppositely polarized.
On the other hand, when performing readout (recalling) from the ferroelectric capacitors F0, F1, the potential at the plate line PL is raised simultaneously with turning ON of the power source. In this case, polarization inversion occurs in either of the pair of ferroelectric capacitors F0, F1, while no polarization inversion occurs in the other ferroelectric capacitor, depending on the polarization conditions. As a result, the effective capacitances of the ferroelectric capacitors F0, F1 differ from each other, causing a difference between the degrees of potential rises in the nodes Q0, Q1, the potential rises being caused by the potential rise in the plate line PL. By resetting the potential at the flip flop 103, utilizing the above difference, the recall operation is completed.
The prior art described above has, however, revealed the following drawbacks. First, ferroelectric substances require high deposition temperature as noted earlier and are vulnerable to reduction atmosphere. Therefore, there arises a need for additional processes such as an etching process in the fabrication of a device, an oxidation process after a hydrogen reduction process, and formation of barrier layers for preventing reduction caused by hydrogen. This leads not only to an increase in the production cost but also to a failure in miniaturization.
Secondly, there is a need to control a voltage to be applied to each ferroelectric substance. Generally, polarization inversion occurs if the electric field of the ferroelectric substance exceeds a certain threshold electric field (coercive electric field), and this polarization condition is utilized to determine whether or not data exists. However, polarization inversion sometimes occurs even when the electric field does not exceed the coercive electric field. Therefore, if a voltage is applied to each ferroelectric substance in other occasions than the store operation and the recall operation, the polarization condition slightly changes in some cases even if the electric field of the ferroelectric substance is no more than the coercive electric field. If such a change in the polarization condition is repeated, the polarization condition is destroyed. This is the phenomenon called “disturb”. To avoid “disturb”, the voltage applied to each ferroelectric substance needs to be controlled.
In cases where the nodes Q0, Q1 of the flip flop 103 are directly connected to the ferroelectric capacitors F0, F1 respectively as shown in FIG. 13, the wiring capacity of each node Q0 (Q1) increases. In addition, during the operation of the flip flop 103, an electric field is applied to each node Q0 (Q1) by way of the ferroelectric capacitor F0 (F1), the plane line PL and another ferroelectric capacitor. Therefore, a leak current exists in these routes. Generally, a ferroelectric capacitor generates a leak current greater than those of insulating films and interlayer films used for a silicon device composed of, for instance, SiO2. During the operation of the flip flop 103, the polarization of the nodes Q0, Q1 is frequently inverted so that a leak current is generated in a forward direction or reverse direction whenever the polarization of the nodes is inverted.
Fourthly, since it is necessary to fixedly set the plate line PL to ½Vcc even during the operation of the flip flop under normal operating conditions, satisfactory power saving cannot be achieved.